The use of differential architectures is common in a wide range of circuits including comparators, amplifiers, and current mode logic (CML). One major limitation of differential transistor pairs is offset which results from process, environment, and operation variations. For example, offset in differential transistor pairs can come from threshold voltage mismatch due random dopant variation during fabrication. In some cases, such as silicon-on-insulator (SOI) transistors, offset may also result from changes in body voltage depending on the device operation, in a phenomenon generally referred to as the body history effect. The problem is that inaccuracies in differential circuits result in an output that is incorrect. The inaccuracies result from manufacturing variations, shifts in operation etc.
Historically, offset in differential transistor pairs has been addressed in sensitive circuits by either using larger devices (to average out random variations and thus reduce offset) or by implementing offset cancellation circuitry. However, large transistors have greater parasitic capacitance, which tends to degrade circuit performance, and are costly to manufacture due to the increased area required to produce them.
The known solutions for implementing offset cancellation circuitry tend to degrade circuit performance. One common solution involves using the differential pair in a closed-loop feedback configuration, and storing the offset voltage on a capacitor, which is then inserted in series with one of the inputs, so that the input-referred offset is cancelled. The primary disadvantage of this technique is that the circuit must be stable when in feedback configuration, which generally requires that the maximum operating frequency be reduced significantly. Offset can also be cancelled using open-loop techniques, in which the inputs are typically shorted together and the circuit is iteratively adjusted until the output indicates that the offset has been reduced below a given threshold. However, known open-loop calibration circuit solutions generally require the addition of circuit elements in the signal path, which tends to reduce the maximum operating frequency of the system.
There is a need for robust methods and structures for offset cancellation which do not degrade the performance of the circuit or significantly increase the area consumed by the circuit.